Jorge Mart铆nez, Ph.D.
Department of Mathematics and Computer Science
Education
Ph.D. Computer Science, Universidad Antonio de Nebrija, Madrid (Spain)
M.S. Computer Science, Universidad Complutense de Madrid (Spain)
Practice Areas
- Fault tolerance and reliability
Publications and Media Placements
P. Reviriego, S. Pontarelli, J. Mart铆nez. Bitwise Signature Comparison: Enabling More
Efficient Similarity Estimation. IEEE Transactions on Emerging Topics in Computing,
(ISSN: 2168-6750), Vol. 11, Issue. 3, pp. 798 - 804, July-Sept. 2023.
P. Reviriego, J. Mart铆nez, O. Rottenstreich, S. Liu, F. Lombardi. Remove Minimum (RM):
An Error-Tolerant Scheme for Cardinality Estimate by HyperLogLog. Transactions on
Dependable and Secure Computing, (ISSN: 1545-5971), Vol. 19, No. 2, pp. 966-977, March-April
2022.
P. Reviriego, J. Mart铆nez, M. Ottavi. Soft Error Tolerant Count Min Sketches. IEEE
Transactions on Computers, (ISSN: 0018-9340), Vol. 70, No. 2, pp. 284-290, Feb. 2021.
P. Reviriego, J. Mart铆nez, S. Pontarelli. Cuckoo Filters and Bloom Filters: Comparison
and Application to Packet Classification. IEEE Transactions on Network and Service
Management, (ISSN: 1932-4537), Vol. 17, No. 14, pp. 2690-2701, Sept. 2020.
P. Reviriego, J. Mart铆nez, S. Pontarelli. Improving Packet Flow Counting with Fingerprint
Counting. IEEE Communications Letters, (ISSN: 1089-7798), Vol. 24, No. 1, pp. 76-80,
Jan. 2020.
P. Reviriego, J. Mart铆nez, S. Pontarelli. CFBF: Reducing the Insertion Time of Cuckoo
Filters with an Integrated Bloom Filter. IEEE Communications Letters, (ISSN: 1089-7798),
Vol. 23, No. 10, pp. 1857-1861, Oct. 2019.
J. Mart铆nez, P. Reviriego, S. Pontarelli. Accelerating Packet Classification with
Two Class Cuckoo Filters (TC-CF). Sixth International Conference on Software Defined
Systems (SDS 2019), Rome (Italy). June 10-13, 2019.
J. Martinez, M. Atamaner, P. Reviriego, O. Ergin, M. Ottavi, Opcode Vector: An Efficient
Scheme to Detect Soft Errors in Instructions, Microelectronics Reliability, Vol. 86,
pp. 92-97, July 2018.
J. Martinez, J.A. Maestro, P. Reviriego, Evaluating the Impact of the Instruction
Set on Microprocessor Reliability to Soft Errors, IEEE Transactions on Device and
Materials Reliability (ISSN: 1530-4388), Vol. 18, No. 1, March 2018.
J. Mart铆nez, J.A. Maestro, P. Reviriego, A Generalized Scheme to Enhance Error Detection
in the Instruction Set Architecture, Design of Circuits and Integrated Systems Conference
(DCIS 2017), Barcelona (Spain), Nov. 22-24, 2017.
J. Mart铆nez, J.A. Maestro, P. Reviriego, A Scheme to Improve the Intrinsic Error Detection
of the Instruction Set Architecture, IEEE Computer Architecture Letters (ISSN: 1556-6056),
Vol. 16, No. 2, pp. 103-106, July-Dec. 2017.
P. Reviriego, J. Mart铆nez, S. Pontarelli, J.A. Maestro, A Method to Design SEC-DED-DAEC
codes with Optimized Decoding, IEEE Transactions on Device and Materials Reliability
(ISSN: 1530-4388), Vol. 14, No. 3, pp. 884-889, Sept. 2014.